1. Field of the Invention
The present invention relates to an information processing device including a memory management device managing an access from a processor to a memory and a memory management method.
2. Description of the Related Art
A conventional micro processing unit (MPU) uses a dynamic random access memory (DRAM) as a main memory (main storage). Moreover, the conventional MPU uses, for example, a flash memory as a secondary memory device. The conventional MPU and the flash memory are connected together via an I/O interface. The flash memory is treated as a file memory by the MPU.
Conventionally, a management function of a NAND type flash memory is built into a file system.
When the MPU is provided with a cache memory, the DRAM is used as the main memory, and the MPU accesses the NAND type flash memory, an operation is carried out according to the following memory hierarchy in the conventional case.
First, the MPU converts a logical address to a physical address using a memory management unit (MMU) to make an access to a cache memory.
In this case, the MPU accesses the main memory, that is, DRAM, with respect to partial data by virtual memory management of an operating system (OS).
If the MPU further has a need to access the NAND type flash memory, the MPU makes following controls to determine a physical location of the NAND type flash memory by a Flash File System. One is control for avoiding a defective block in NAND type flash memory. Another is control for making accesses to all blocks of the NAND type flash memory almost equally (without difference).
The MPU accesses the NAND type flash memory based on the determined physical location.
In the conventional MPU, when there are many layers of a memory hierarchy, there are many operations which is included in the different layers of the memory hierarchy. It is difficult to effect optimization between operations in difference layers. For example, it is difficult to realize control of managing bad block peculiar to the NAND type flash memory when the MPU makes a changeover of data of the cache memory. Because the control of managing bad block and the changeover of the data of the cache memory are belong to different layers of the memory hierarchy.
When the MPU accesses a file in the secondary memory device, the conventional operating system (OS) needs to perform a great amount of processing. In an information processing device in which a storage capacity of a main memory is small, the number of times of access of the MPU to the secondary memory device such as a hard disk (HDD) or a solid state drive (SSD) is great, so that the number of processes for a program may increase, and processing time may increase.
In order to solve such a problem, the following method is used in, for example, a mobile device; a DRAM having the same capacity as the NAND type flash memory is prepared so that the whole data in the NAND type flash memory is transferred to the DRAM at the start of operation.
However, an expensive DRAM having the same capacity as the inexpensive NAND type flash memory needs to be installed in this method. Thus, this method is easily applied to a device having a low-capacity memory such as a mobile device, but is not easily applied to other device having greater storage capacity.
A document 1 (Jpn. Pat. Appln. KOKAI Publication No. 2008-242944) has proposed an integrated memory management device. In this integrated memory management device, a NAND type flash memory is used as a main memory for an MPU. Further, in the document 1, a primary cache memory, a secondary cache memory and the NAND type flash memory as the main memory in the MPU are treated in a same memory layer. A cache controller of the integrated memory management device performs the management of the main memory in addition to the management of the primary cache memory and the secondary cache memory.
A document 2 (Jpn. Pat. Appln. KOKAI Publication No. 7-146820) discloses a technique for employing a flash memory as a main memory of an information processing device. In the document 2, the flash memory is connected to a memory bus of a system via a cache memory which is a nonvolatile memory. The cache memory is provided with an address array for recording information including, for example, addresses or access histories of data stored in this cache memory. A controller refers to the address to access, and supplies data in the cache memory or flash memory to the memory bus or stores data in the memory bus.
A document 3 (Jpn. Pat. Appln. KOKAI Publication No. 2001-266580) discloses an invention enable different kind of semiconductor memory devices to be connected to a common bus.
The semiconductor memory device disclosed in the document 3 includes a random access memory chip and a package having the random access memory chip. The package comprises a plurality of pins electrically connecting the random access memory chip to an external device. The pins provide a memory function in common to a random access memory and an electrically erasable and programmable non-volatile semiconductor memory. The pins are arrayed according to the corresponding pin position of the non-volatile semiconductor memory.